A REVIEW OF WALLACE TREE MULTIPLIER USING ADIABATIC LOGIC

Abstract

Wallace Tree Multiplier (WTM) is one of the fastest multiplier used in many data-processing processors to perform fast arithmetic functions. From the structure of the RCWM (Reduced Complexity Wallace Tree Multiplier), it is clear that there is scope for reducing the area and power consumption. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of WTM. Conventional WTM is still area-consuming due to the CMOS switching structure. The logic operations involved in conventional RCWM and WTM are analyzed to study the data dependence and to identify redundant logic operations. RCWM reduced number of half adders used in Standard Wallace Multiplier (SWM) with a slight increase in full adders to reduce the number of gates. Adiabatic Logic eliminated all the redundant logic operations present in conventional RCWM. Experimental analysis shows that this architecture achieves the three folded advantages in terms of area and power.