DESIGN OF 8 X 8 VEDIC MULTIPLIER USING QUATERNARY-LOGIC & PIPELINING ARCHITECTURE

Abstract

In recent years the growth of the portable electronic is forcing the designers to optimize the existing design for better performance. There are different entities that one would like to optimize when designing a VLSI circuit. These entities can often not be optimized simultaneously, only improve one entity at the expense of one or more others. A multiplication is the important operation used in various applications like DSP processor, math processor and in various arithmetic circuits. In VLSI system the overall performance is strongly depends on the performance of arithmetic circuits like multiplier. Designers find the solution of these by implementing technique of calculation based on Indian Vedas mathematics called as Vedic multiplier, which offers simple way of multiplication. The design of an efficient multiplier circuit in terms of power, area, and speed simultaneously, has become a very challenging problem. Power dissipation is recognized as a critical parameter in modern VLSI design field. The multi valued logic (MVL) provides the key benefit of a higher density per integration circuit area compared to traditional two valued binary logic. All so the Quaternary logic offers the benefit of easy interfacing to binary logic because radix 4 allow for the use of simple encoding/decoding circuits. This paper present design of 8x8 Vedic multiplier using Tanner EDA tool & simulated using T-spice simulator. With the help of pipelining technique 8x8 Vedic multiplier circuit level has been proposed in these paper, as it does not increase the hardware that much, but which increase the speed and requires less computation gives us better speed. The two stages pipelining is used to optimize Delay compared with previously normal 8x8 Vedic multiplier results.